00001
00002 /***************************************************************************
00003  *  mmx.h - MMX CPU extension support
00004  *
00005  *  Copyright  1997-2001  H. Dietz and R. Fisher (copied form FFmpeg)
00006  *
00007  ****************************************************************************/
00008
00009 /*  This program is free software; you can redistribute it and/or modify
00010  *  it under the terms of the GNU General Public License as published by
00011  *  the Free Software Foundation; either version 2 of the License, or
00012  *  (at your option) any later version.
00013  *
00014  *  This program is distributed in the hope that it will be useful,
00015  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00016  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017  *  GNU Library General Public License for more details.
00018  *
00019  *  Read the full text in the LICENSE.GPL file in the doc directory.
00020  */
00021
00022 #ifndef __FIREVISION_FVUTILS_CPU_MMX_H_
00023 #define __FIREVISION_FVUTILS_CPU_MMX_H_
00024 
00025 /// @cond MMX
00026 
00027 /*
00028  * The type of an value that fits in an MMX register (note that long
00029  * long constant values MUST be suffixed by LL and unsigned long long
00030  * values by ULL, lest they be truncated by the compiler)
00031  */
00032
00033 typedef        union {
00034         long long               q;      /* Quadword (64-bit) value */
00035         unsigned long long      uq;     /* Unsigned Quadword */
00036         int                     d[2];   /* 2 Doubleword (32-bit) values */
00037         unsigned int            ud[2];  /* 2 Unsigned Doubleword */
00038         short                   w[4];   /* 4 Word (16-bit) values */
00039         unsigned short          uw[4];  /* 4 Unsigned Word */
00040         char                    b[8];   /* 8 Byte (8-bit) values */
00041         unsigned char           ub[8];  /* 8 Unsigned Byte */
00042         float                   s[2];   /* Single-precision (32-bit) value */
00043 } mmx_t;        /* On an 8-byte (64-bit) boundary */
00044
00045
00046 #define         mmx_i2r(op,imm,reg) \
00047         __asm__ __volatile__ (#op " %0, %%" #reg \
00048                               : /* nothing */ \
00049                               : "i" (imm) )
00050
00051 #define         mmx_m2r(op,mem,reg) \
00052         __asm__ __volatile__ (#op " %0, %%" #reg \
00053                               : /* nothing */ \
00054                               : "m" (mem))
00055
00056 #define         mmx_r2m(op,reg,mem) \
00057         __asm__ __volatile__ (#op " %%" #reg ", %0" \
00058                               : "=m" (mem) \
00059                               : /* nothing */ )
00060
00061 #define         mmx_r2r(op,regs,regd) \
00062         __asm__ __volatile__ (#op " %" #regs ", %" #regd)
00063 
00064
00065 #define         emms() __asm__ __volatile__ ("emms")
00066 
00067 #define         movd_m2r(var,reg)           mmx_m2r (movd, var, reg)
00068 #define         movd_r2m(reg,var)           mmx_r2m (movd, reg, var)
00069 #define         movd_r2r(regs,regd)         mmx_r2r (movd, regs, regd)
00070 
00071 #define         movq_m2r(var,reg)           mmx_m2r (movq, var, reg)
00072 #define         movq_r2m(reg,var)           mmx_r2m (movq, reg, var)
00073 #define         movq_r2r(regs,regd)         mmx_r2r (movq, regs, regd)
00074 
00075 #define         packssdw_m2r(var,reg)       mmx_m2r (packssdw, var, reg)
00076 #define         packssdw_r2r(regs,regd)     mmx_r2r (packssdw, regs, regd)
00077 #define         packsswb_m2r(var,reg)       mmx_m2r (packsswb, var, reg)
00078 #define         packsswb_r2r(regs,regd)     mmx_r2r (packsswb, regs, regd)
00079 
00080 #define         packuswb_m2r(var,reg)       mmx_m2r (packuswb, var, reg)
00081 #define         packuswb_r2r(regs,regd)     mmx_r2r (packuswb, regs, regd)
00082 
00083 #define         paddb_m2r(var,reg)          mmx_m2r (paddb, var, reg)
00084 #define         paddb_r2r(regs,regd)        mmx_r2r (paddb, regs, regd)
00085 #define         paddd_m2r(var,reg)          mmx_m2r (paddd, var, reg)
00086 #define         paddd_r2r(regs,regd)        mmx_r2r (paddd, regs, regd)
00087 #define         paddw_m2r(var,reg)          mmx_m2r (paddw, var, reg)
00088 #define         paddw_r2r(regs,regd)        mmx_r2r (paddw, regs, regd)
00089 
00090 #define         paddsb_m2r(var,reg)         mmx_m2r (paddsb, var, reg)
00091 #define         paddsb_r2r(regs,regd)       mmx_r2r (paddsb, regs, regd)
00092 #define         paddsw_m2r(var,reg)         mmx_m2r (paddsw, var, reg)
00093 #define         paddsw_r2r(regs,regd)       mmx_r2r (paddsw, regs, regd)
00094 
00095 #define         paddusb_m2r(var,reg)        mmx_m2r (paddusb, var, reg)
00096 #define         paddusb_r2r(regs,regd)      mmx_r2r (paddusb, regs, regd)
00097 #define         paddusw_m2r(var,reg)        mmx_m2r (paddusw, var, reg)
00098 #define         paddusw_r2r(regs,regd)      mmx_r2r (paddusw, regs, regd)
00099 
00100 #define         pand_m2r(var,reg)           mmx_m2r (pand, var, reg)
00101 #define         pand_r2r(regs,regd)         mmx_r2r (pand, regs, regd)
00102 
00103 #define         pandn_m2r(var,reg)          mmx_m2r (pandn, var, reg)
00104 #define         pandn_r2r(regs,regd)        mmx_r2r (pandn, regs, regd)
00105 
00106 #define         pcmpeqb_m2r(var,reg)        mmx_m2r (pcmpeqb, var, reg)
00107 #define         pcmpeqb_r2r(regs,regd)      mmx_r2r (pcmpeqb, regs, regd)
00108 #define         pcmpeqd_m2r(var,reg)        mmx_m2r (pcmpeqd, var, reg)
00109 #define         pcmpeqd_r2r(regs,regd)      mmx_r2r (pcmpeqd, regs, regd)
00110 #define         pcmpeqw_m2r(var,reg)        mmx_m2r (pcmpeqw, var, reg)
00111 #define         pcmpeqw_r2r(regs,regd)      mmx_r2r (pcmpeqw, regs, regd)
00112 
00113 #define         pcmpgtb_m2r(var,reg)        mmx_m2r (pcmpgtb, var, reg)
00114 #define         pcmpgtb_r2r(regs,regd)      mmx_r2r (pcmpgtb, regs, regd)
00115 #define         pcmpgtd_m2r(var,reg)        mmx_m2r (pcmpgtd, var, reg)
00116 #define         pcmpgtd_r2r(regs,regd)      mmx_r2r (pcmpgtd, regs, regd)
00117 #define         pcmpgtw_m2r(var,reg)        mmx_m2r (pcmpgtw, var, reg)
00118 #define         pcmpgtw_r2r(regs,regd)      mmx_r2r (pcmpgtw, regs, regd)
00119 
00120 #define         pmaddwd_m2r(var,reg)        mmx_m2r (pmaddwd, var, reg)
00121 #define         pmaddwd_r2r(regs,regd)      mmx_r2r (pmaddwd, regs, regd)
00122 
00123 #define         pmulhw_m2r(var,reg)         mmx_m2r (pmulhw, var, reg)
00124 #define         pmulhw_r2r(regs,regd)       mmx_r2r (pmulhw, regs, regd)
00125 
00126 #define         pmullw_m2r(var,reg)         mmx_m2r (pmullw, var, reg)
00127 #define         pmullw_r2r(regs,regd)       mmx_r2r (pmullw, regs, regd)
00128 
00129 #define         por_m2r(var,reg)            mmx_m2r (por, var, reg)
00130 #define         por_r2r(regs,regd)          mmx_r2r (por, regs, regd)
00131 
00132 #define         pslld_i2r(imm,reg)          mmx_i2r (pslld, imm, reg)
00133 #define         pslld_m2r(var,reg)          mmx_m2r (pslld, var, reg)
00134 #define         pslld_r2r(regs,regd)        mmx_r2r (pslld, regs, regd)
00135 #define         psllq_i2r(imm,reg)          mmx_i2r (psllq, imm, reg)
00136 #define         psllq_m2r(var,reg)          mmx_m2r (psllq, var, reg)
00137 #define         psllq_r2r(regs,regd)        mmx_r2r (psllq, regs, regd)
00138 #define         psllw_i2r(imm,reg)          mmx_i2r (psllw, imm, reg)
00139 #define         psllw_m2r(var,reg)          mmx_m2r (psllw, var, reg)
00140 #define         psllw_r2r(regs,regd)        mmx_r2r (psllw, regs, regd)
00141 
00142 #define         psrad_i2r(imm,reg)          mmx_i2r (psrad, imm, reg)
00143 #define         psrad_m2r(var,reg)          mmx_m2r (psrad, var, reg)
00144 #define         psrad_r2r(regs,regd)        mmx_r2r (psrad, regs, regd)
00145 #define         psraw_i2r(imm,reg)          mmx_i2r (psraw, imm, reg)
00146 #define         psraw_m2r(var,reg)          mmx_m2r (psraw, var, reg)
00147 #define         psraw_r2r(regs,regd)        mmx_r2r (psraw, regs, regd)
00148 
00149 #define         psrld_i2r(imm,reg)          mmx_i2r (psrld, imm, reg)
00150 #define         psrld_m2r(var,reg)          mmx_m2r (psrld, var, reg)
00151 #define         psrld_r2r(regs,regd)        mmx_r2r (psrld, regs, regd)
00152 #define         psrlq_i2r(imm,reg)          mmx_i2r (psrlq, imm, reg)
00153 #define         psrlq_m2r(var,reg)          mmx_m2r (psrlq, var, reg)
00154 #define         psrlq_r2r(regs,regd)        mmx_r2r (psrlq, regs, regd)
00155 #define         psrlw_i2r(imm,reg)          mmx_i2r (psrlw, imm, reg)
00156 #define         psrlw_m2r(var,reg)          mmx_m2r (psrlw, var, reg)
00157 #define         psrlw_r2r(regs,regd)        mmx_r2r (psrlw, regs, regd)
00158 
00159 #define         psubb_m2r(var,reg)          mmx_m2r (psubb, var, reg)
00160 #define         psubb_r2r(regs,regd)        mmx_r2r (psubb, regs, regd)
00161 #define         psubd_m2r(var,reg)          mmx_m2r (psubd, var, reg)
00162 #define         psubd_r2r(regs,regd)        mmx_r2r (psubd, regs, regd)
00163 #define         psubw_m2r(var,reg)          mmx_m2r (psubw, var, reg)
00164 #define         psubw_r2r(regs,regd)        mmx_r2r (psubw, regs, regd)
00165 
00166 #define         psubsb_m2r(var,reg)         mmx_m2r (psubsb, var, reg)
00167 #define         psubsb_r2r(regs,regd)       mmx_r2r (psubsb, regs, regd)
00168 #define         psubsw_m2r(var,reg)         mmx_m2r (psubsw, var, reg)
00169 #define         psubsw_r2r(regs,regd)       mmx_r2r (psubsw, regs, regd)
00170 
00171 #define         psubusb_m2r(var,reg)        mmx_m2r (psubusb, var, reg)
00172 #define         psubusb_r2r(regs,regd)      mmx_r2r (psubusb, regs, regd)
00173 #define         psubusw_m2r(var,reg)        mmx_m2r (psubusw, var, reg)
00174 #define         psubusw_r2r(regs,regd)      mmx_r2r (psubusw, regs, regd)
00175 
00176 #define         punpckhbw_m2r(var,reg)      mmx_m2r (punpckhbw, var, reg)
00177 #define         punpckhbw_r2r(regs,regd)    mmx_r2r (punpckhbw, regs, regd)
00178 #define         punpckhdq_m2r(var,reg)      mmx_m2r (punpckhdq, var, reg)
00179 #define         punpckhdq_r2r(regs,regd)    mmx_r2r (punpckhdq, regs, regd)
00180 #define         punpckhwd_m2r(var,reg)      mmx_m2r (punpckhwd, var, reg)
00181 #define         punpckhwd_r2r(regs,regd)    mmx_r2r (punpckhwd, regs, regd)
00182 
00183 #define         punpcklbw_m2r(var,reg)      mmx_m2r (punpcklbw, var, reg)
00184 #define         punpcklbw_r2r(regs,regd)    mmx_r2r (punpcklbw, regs, regd)
00185 #define         punpckldq_m2r(var,reg)      mmx_m2r (punpckldq, var, reg)
00186 #define         punpckldq_r2r(regs,regd)    mmx_r2r (punpckldq, regs, regd)
00187 #define         punpcklwd_m2r(var,reg)      mmx_m2r (punpcklwd, var, reg)
00188 #define         punpcklwd_r2r(regs,regd)    mmx_r2r (punpcklwd, regs, regd)
00189 
00190 #define         pxor_m2r(var,reg)           mmx_m2r (pxor, var, reg)
00191 #define         pxor_r2r(regs,regd)         mmx_r2r (pxor, regs, regd)
00192 
00193
00194 /* 3DNOW extensions */
00195
00196 #define         pavgusb_m2r(var,reg)        mmx_m2r (pavgusb, var, reg)
00197 #define         pavgusb_r2r(regs,regd)      mmx_r2r (pavgusb, regs, regd)
00198 
00199
00200 /* AMD MMX extensions - also available in intel SSE */
00201
00202
00203 #define         mmx_m2ri(op,mem,reg,imm) \
00204         __asm__ __volatile__ (#op " %1, %0, %%" #reg \
00205                               : /* nothing */ \
00206                               : "m" (mem), "i" (imm))
00207 #define         mmx_r2ri(op,regs,regd,imm) \
00208         __asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
00209                               : /* nothing */ \
00210                               : "i" (imm) )
00211
00212 #define         mmx_fetch(mem,hint) \
00213         __asm__ __volatile__ ("prefetch" #hint " %0" \
00214                               : /* nothing */ \
00215                               : "m" (mem))
00216
00217
00218 #define         maskmovq(regs,maskreg)      mmx_r2ri (maskmovq, regs, maskreg)
00219 
00220 #define         movntq_r2m(mmreg,var)       mmx_r2m (movntq, mmreg, var)
00221 
00222 #define         pavgb_m2r(var,reg)          mmx_m2r (pavgb, var, reg)
00223 #define         pavgb_r2r(regs,regd)        mmx_r2r (pavgb, regs, regd)
00224 #define         pavgw_m2r(var,reg)          mmx_m2r (pavgw, var, reg)
00225 #define         pavgw_r2r(regs,regd)        mmx_r2r (pavgw, regs, regd)
00226 
00227 #define         pextrw_r2r(mmreg,reg,imm)   mmx_r2ri (pextrw, mmreg, reg, imm)
00228 
00229 #define         pinsrw_r2r(reg,mmreg,imm)   mmx_r2ri (pinsrw, reg, mmreg, imm)
00230 
00231 #define         pmaxsw_m2r(var,reg)         mmx_m2r (pmaxsw, var, reg)
00232 #define         pmaxsw_r2r(regs,regd)       mmx_r2r (pmaxsw, regs, regd)
00233 
00234 #define         pmaxub_m2r(var,reg)         mmx_m2r (pmaxub, var, reg)
00235 #define         pmaxub_r2r(regs,regd)       mmx_r2r (pmaxub, regs, regd)
00236 
00237 #define         pminsw_m2r(var,reg)         mmx_m2r (pminsw, var, reg)
00238 #define         pminsw_r2r(regs,regd)       mmx_r2r (pminsw, regs, regd)
00239 
00240 #define         pminub_m2r(var,reg)         mmx_m2r (pminub, var, reg)
00241 #define         pminub_r2r(regs,regd)       mmx_r2r (pminub, regs, regd)
00242 
00243 #define         pmovmskb(mmreg,reg) \
00244         __asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg)
00245 
00246 #define         pmulhuw_m2r(var,reg)        mmx_m2r (pmulhuw, var, reg)
00247 #define         pmulhuw_r2r(regs,regd)      mmx_r2r (pmulhuw, regs, regd)
00248 
00249 #define         prefetcht0(mem)             mmx_fetch (mem, t0)
00250 #define         prefetcht1(mem)             mmx_fetch (mem, t1)
00251 #define         prefetcht2(mem)             mmx_fetch (mem, t2)
00252 #define         prefetchnta(mem)            mmx_fetch (mem, nta)
00253 
00254 #define         psadbw_m2r(var,reg)         mmx_m2r (psadbw, var, reg)
00255 #define         psadbw_r2r(regs,regd)       mmx_r2r (psadbw, regs, regd)
00256 
00257 #define         pshufw_m2r(var,reg,imm)     mmx_m2ri(pshufw, var, reg, imm)
00258 #define         pshufw_r2r(regs,regd,imm)   mmx_r2ri(pshufw, regs, regd, imm)
00259 
00260 #define         sfence() __asm__ __volatile__ ("sfence\n\t")
00261 
00262 /* SSE2 */
00263 #define         pshufhw_m2r(var,reg,imm)    mmx_m2ri(pshufhw, var, reg, imm)
00264 #define         pshufhw_r2r(regs,regd,imm)  mmx_r2ri(pshufhw, regs, regd, imm)
00265 #define         pshuflw_m2r(var,reg,imm)    mmx_m2ri(pshuflw, var, reg, imm)
00266 #define         pshuflw_r2r(regs,regd,imm)  mmx_r2ri(pshuflw, regs, regd, imm)
00267 
00268 #define         pshufd_r2r(regs,regd,imm)   mmx_r2ri(pshufd, regs, regd, imm)
00269 
00270 #define         movdqa_m2r(var,reg)         mmx_m2r (movdqa, var, reg)
00271 #define         movdqa_r2m(reg,var)         mmx_r2m (movdqa, reg, var)
00272 #define         movdqa_r2r(regs,regd)       mmx_r2r (movdqa, regs, regd)
00273 #define         movdqu_m2r(var,reg)         mmx_m2r (movdqu, var, reg)
00274 #define         movdqu_r2m(reg,var)         mmx_r2m (movdqu, reg, var)
00275 #define         movdqu_r2r(regs,regd)       mmx_r2r (movdqu, regs, regd)
00276 
00277 #define         pmullw_r2m(reg,var)         mmx_r2m (pmullw, reg, var)
00278 
00279 #define         pslldq_i2r(imm,reg)         mmx_i2r (pslldq, imm, reg)
00280 #define         psrldq_i2r(imm,reg)         mmx_i2r (psrldq, imm, reg)
00281 
00282 #define         punpcklqdq_r2r(regs,regd)   mmx_r2r (punpcklqdq, regs, regd)
00283 #define         punpckhqdq_r2r(regs,regd)   mmx_r2r (punpckhqdq, regs, regd)
00284 
00285 /// @endcond
00286 
00287 #endif